High Density Interconnect (HDI) Printed Circuit Board (PCB)

 

PCB technology has been evolving with changing technology that calls for smaller and faster products. High-density interconnect (HDI) PCB technology, including laser drill micro-vias, VIP (Via-in-Pad), blind and/or buried vias and build-up laminations, is one of the most significant advances in PCB manufacturing. HDI printed circuit boards (PCBs) are with a higher wiring density per unit area than traditional PCBs. Products with HDI PCBs are more compact and have smaller vias, pads, and traces and spaces. As a result, HDI board can house the functionality of the previous boards used. MADPCB is an HDI PCB manufacturer and provider in Shenzhen, supports HDI PCB prototype and mass production with less expensive price and quick-turn lead time. Customers from a variety of industries we serve have a common that have high expectations in quality, reliability and on-time delivery in HDI PCB production. Our quality is not afterthought, but built into each process from front-end to fabrication and shipping.


HDI PCB Manufacturing Process

The overall process for manufacturing HDI PCB is essentially the same as for fabricating other PCB board, with notable differences for PCB stack-up and hole drilling. Since HDI boards generally require smaller drill holes for vias, laser drilling is usually required. Although laser drills can produce smaller and more precise holes, they are limited by depth. Therefore, a limited number of layers can be drilled through at a time. For HDI boards, which are invariably multilayer and may contain buried and blind vias, multiple drilling processes may be required. This necessitates successive layer boding to achieve the desired stack-up or sequential lamination cycles. Not surprisingly, this can significantly increase PCB manufacturing time and cost.

HDI PCB fabrication is an advanced technology and therefore requires expertise along with specialized equipment like laser drills, laser direct imaging (LDI) capacity, and special clean room environments. In order to efficiently manufacture high-quality and reliable HDI PCB products, you must understand the HDI board manufacturing process and coordinate with your HDI PCB supplier and provider to implement good DFM (Design for Manufacturability) for HDI layout.

 

HDI PCB Design

The electronics industry is largely consumer-driven and the directive for smaller more capable products with increased functionality will only intensify in the years to come. At MADPCB, we are well-positioned to assist you in meeting this demand with advanced equipment, processes and expertise to manufacture your HDI PCB boards quickly and precisely. Click to learn more of our Design for HDI PCBs.

HDI Board Stack-up

  • 1+N+1 with laser microvia and mechanical buried core via. The “1” represents “build-up” or sequential lamination on each side of the core.

  • i+N+i (i>=2) – PCBs contain 2 or more “build-up” of high-density interconnect layers. Microvias on different layers can be staggered or stacked. Copper filled stacked microvia structures are commonly seen in challenging designs.

  • Any Layer HDI (ELIC) – All the layers of a PCB are high-density interconnection layers which allows the conductors on any layer of the PCB to be interconnected freely with copper filled stacked microvia structures (“any layer via”). This provides a reliable interconnect solution for highly complex large pin-count devices, such as CPU and GPU chips utilized on handheld and mobile devices.


HDI PCB Types

 There are 6 common HDI Construction Types.

Type

Core / Passive

Definition

Type I

1 [C] 0 or 1 [C] 1

Type I construction describes an HDI board in which there are both microvias and conductive vias used for interconnection. Type I constructions describe the fabrication of a single microvia layer on either one (1 [C] 0) or both (1 [C] 1) sides of a PCB substrate core.

Type II

2[C] 0 or 1 [C] 1

Type II construction describes an HDI PCB in which there are plated microvias, plated buried vias, and may have PTHs used for surface-to-surface interconnection. The buried vias may be prefilled with a conductive/non-conductive paste or partially or completely filled with dielectric material from the lamination process.

Type III

2 [C]0

Type III construction describes an HDI PCB board in which there are plated microvias, plated buried vias, and may have PTHs used for surface-to-surface interconnection. The buried vias may be prefilled with a conductive/non-conductive paste or partially or completely filled with dielectric material from the lamination process.

Type IV

1 [P]0

Type IV construction describes an HDI circuit board in which the microvia layers are used over an existing predrilled passive substrate. Additional microvia layers can be added sequentially. The core substrate is usually manufactured using conventional printed board techniques. The function of the core is passive, yet it may be used for thermal, CTE management, or shielding (the core doesn’t perform an electrical function).

Type V

Coreless (Layer Pairs)

Type V construction describes an HDI printed circuit board in which there are both plated microvias and conductive paste interconnections through a co-lamination process. There is essentially no core to this type of construction since all layer pairs have the same characteristics. Type V construction consists of the HDI PCB fabrication of an even number of layers that are laminated together at the same time the interconnections are made between the odd and even layers. This type of construction is neither build-up nor sequential; it it a single lamination process.

Type VI


Type VI construction describes an HDI printed board in which the electrical interconnection and mechanical structure are formed simultaneously. The layers may be formed sequentially or co-laminated, and the conductive interconnection may be formed by means other than electroplating (i.e. anisotrophic films/pastes, conductive paste, dielectric piercing posts, etc.)

 

Figure 1: Type I HDI Construction


Figure 2: Type II HDI Construction

Figure 3-1: Type III HDI Construction (Caution: Unbalanced constructions may result in excessive bow and twist)

Note 1: Caution should be used when placing a microvia above a non-stacked buried via due to z-axis stresses during thermal excusions.


Figure 3-2: Type III HDI Construction with Stacked Microvias (Caution: Unbalanced constructions as shown below may result in excessive bow and twist).

Note 1: Stacking not recommended for resin or non-conductive filled microvias

Note 2: Stacking not recommended over resin or non-conductive filled vias due to potential for reduced reliability. The use of staggered structures instead is recommended.


Figure 3-3: Type III HDI PCB with Staggered Microvias (Caution: Unbalanced constructions may result in warp and twist).


Figure 3-4: Type III with Variable Depth Blind Vias

Note 1: Variable Depth Microvias formed in one operation, spanning two or more dielectric layers.


Figure 4: Type IV HDI Construction


Figure 5: Coreless Type V HDI Construction

Figure 6: Type VI Construction


Microvia (Build-Up Via)

Microvia (Build-up Via) defined as a blind structure (as plated) with maximum aspect ratio of 1:1 when measured in accordance with figure below, terminating on or penetrating a target land, with a total depth (X) of no more than 0.25mm (0.00984 in) measured from the structure capture land foil to the target land.

Capture Land (Via Top Land)

Capture Land defined as the external land portion during formation of a blind or buried microvia. See figure below,

Stacked Microvias

Stacked Microvia is a structure formed by vertically aligning microvias directly on top of each other (or on top of a buried via). See figure below for examples of stacked microvia structures. 9.2.2

Staggered Microvias

Staggered Microvias is a structure formed by offsetting microvias laterally off each other in the vertical direction (or off a buried via). See figures below for examples of stacked microvia structures.


Laser Drilling Technology

Unlike mechanical drills, the laser drilling process doesn’t physically contact the PCB material that it is working with. Drilling the smallest of microvias allows for more technology on the PCB surface. The high influence beam of the laser machine can drill through metal and glass to create the tiny via hole. HDI PCBs always have a large laser drilling quantity per square meter, even more than 50K density since its high-density interconnection, and the laser machine drilling capacity always reaches 4.3million pieces daily.

Laser Drilling Imaging (LDI)

Imaging finer traces than ever before to process these HDI parts is costly but necessary. Finer traces, spacing and annular ring requires much tighter controls. With use of finer traces, touch up rework or repair becomes an impossible task. Photo tool quality, laminate prepreg and imaging parameters are necessary for successful process. LDI (laser direct imaging) is a far better option for such fine traces and spacings.

Via-in-Pad (VIP)

When micrvias are placed in pads intended to be soldered (Via-in-Pad), the holes should be filled. Vias can be filled and plated over or filled with copper to yield an acceptable solderable surface. If the vias are not filled, the volume of the microvia will “steal” solder from the intended solder joint. The air, which is entrapped after solder paste has been applied, is also likely to out gas during the reflow assembly process and create voids in the solder joints.

In PCB design, via refers to a pad with a plated hole that connects copper tracks from one layer of the board to other layer(s). High-density multi-layer PCBs may have blind vias, which are visible only on one surface, or buried vias, which are visible o neither, normally referred to as micro vias. The advent and extensive use of finer pitch devices or products and requirements for smaller size PCBs creates new challenges. An exciting solution to these challenges uses a recent, but common PCB manufacturing technology with self-descriptive name, “VIA IN PAD”.

Via in pad helps to reduce inductance, increase density and employ finer pitch array packages. The via in pad approach places a via directly under the device’s contact pads. This allows higher component density and improved routing. Consequently, via in pad provides the designer significant PCB space savings. For example, traditional fan-out places four components, whereas with via in pad, eight components can be placed within the same board outline.

Filled via in pad is a way to achieve intermediate density with an intermediate cost compared to using blind or buried vias. Some of the key advantages associated with using the via in pad technology are:

  • Fan out fine pitch (less than 3mil) BGAs

  • Meets closely packed placement requirements

  • Better thermal management

  • Overcomes high speed design issues and constraints i.e. low inductance

  • No via plugging is required at component locations

  • Provides a flat, coplanar surface for component attachment

However, there are some disadvantages associated with this technology. The most prominent and worrisome is the cost impact associated with adopting a new technology. PCB manufacturers and suppliers identified two primary cost drivers associated with specifying via in pad technology: Additional HDI PCB manufacturing process complexity and the underlying material cost for the conductive fill.

Specifically, via in pad technology adds 8 to 10 steps to the PCB manufacturing process while via filling cost is a function of the via size and actual number of via instances on any given design. However, the reduction in layer count realized by using via in pad technology compensates for the added cost associated with this process.

 

HDI PCB Materials Selection

Material type and construction is extremely important in designing and manufacturing HDI PCB boards. Designing HDI interconnects involves an understanding of the potential problems arising when specifying glass reinforced dielectric materials.

Microvia dielectric materials can introduce misregistration and rough vias whether plasma, laser, or mechanical drilling is performed. Not only are the material properties of the microvia dielectric materials called into question, but also the consistency of the weave, as well as the quality of the fibers used. The potential to close the weave openings by spreading the fibers out is extremely important, as this minimizes open spaces that cause skew and drift.

  • Copper Clad Laminate (CCL): Copper clad laminate materials have copper foil laminated onto one or both sides of cured (C-stage) dielectric. The typical application uses single-side clad laminate material where the copper clad is used as the outer layer and the c-stage is bonded to the sub-composite. Microvia are formed utilizing plasma or laser methods. Materials available differ by reinforcement (woven glass, non-woven glass and expanded PTFE) and chemistries involved (epoxies, polyimide, polyester etc.).

  • Resin Coated Copper (RCC): Resin coated copper materials are compromised of copper foil, coated with a resin dielectric material that can be directly bonded to the sub-composite. They differ by whether they are wet processable or not. In non-wet processable-coated copper materials, microvias are formed utilizing plasma or laser drilling methods.

  • Embedded Electronics Components: Passive components, such as resistors, capacitors and inductors, as well as active components, are referred to as embedded components when placed withing the substrate of the thru-hole and HDI printed circuit board. These are known as Embedded Resistor PCB, Embedded Capacitor PCB, Embedded Inductor PCB or Embedded XX PCB. A wide variety of materials and methods can be used when embedding these circuit functions within the PCB board, and there are a number of reasons why designers would want to embed components within an HDI printed board. The primary reason is related to circuit function. In digital circuits clock rate drive the signal rise time. In analog circuits bandwidth drives signal rise times. As signal rise times decrease and corresponding frequencies increase, the lead inductance associated with discrete, surface mount components begins to degrade circuit function. Moving the component from the surface of the HDI PCB into the substrate reduces the lead inductance and parasitic capacitance. Secondary considerations for embedding components are related to PCB surface real estate and subsequent cost. As frequencies go up and circuits become more complex, more passives are needed to maintain signal integrity. Increased PCB size adds cost while consumer pressure demands smaller and less costly products. Embedded components in the printed board frees surface real estate for more functionality and enables PCB board size reduction with corresponding cost reduction. Finally, a third level of impetus to embed components is reduction of the overall number of solder joint connections, which could improve overall reliability of the PCB board.

  1. Embedded Resistor PCB: Embedded resistors are formed within the substrate of the printed circuit board by any of several methods. The resistive elements are typically formed between two conductors on the same layer. Resistor chemistries include Nickel/Phosphorus, Lanthanum Boride, Mixed Metal in Organic Matrix, Conductive Polymer, Doped Platinum, Organometallic, Nickel/Chromium, and Nickel/Chromium/Aluminum Silicon. Some embedded resistors have an encapsulant applied above, below or both. The encapsulant materials are typically epoxy based.

  2. Embedded Capacitor PCB: Embedded capacitors are formed within the substrate of the printed circuit board by any of several methods. There are two distinct differences among embedded capacitor materials. One type is in the form of an inner layer laminate comprised of a dielectric core having copper or other form of conductor on both sides of the core. The copper or other form of conductor on each side of the dielectric forms the two plates of the capacitor. The other type is dielectric applied in discrete locations on a layer with the copper or other conductor initially existing on that layer forming one plate of the capacitor and a copper or silver-based paste applied as the second electrode. Some embedded capacitors have an encapsulant applied.

  3. Embedded Inductor PCB: Embedded inductors are typically made by imaging the copper on one or more layers within the printed circuit board in spiral patterns, Inductors are also made by applying a ferromagnetic material above, below or between the spiral conductor patterns.


Typical Feature Sizes for HDI PCB Construction


ASPECT RATIO

Level A

Level B

Level C


Microvia plating aspect ratio

0.5:1

(K + j) / b

0.5:1 to 0.85:1

(K + j) / b

0.85:1

(K + j) / b


Through via hole aspect ratio3

8:1

(2K + u) / h

8:1 to 10:1

(2K + u) / h

10:1

(2K + u) / h


Buried via aspect ratio3

8:1

(2r + q) / h

8:1 to 10:1

(2r + q) / h

10:1

(2r + q) / h

Symbol

Feature

Level A

Level B

Level C

a

Microvia diameter at target land

(as formed, no plating)

b/2

b/2

b/2

b

Microvia diameter at capture land

(as formed, no plating)

150μm [6mil]

100μm [4mil]

75μm [3mil]

c4

Process 2 from Figure 9-1

Microvia target land size =

[(b + 2X min annular ring) + FA(1)]

300μm [12mil]

225μm [9mil]

175μm [7mil]

Microvia FA

150μm [6mil]

125μm [5mil]

100μm [4mil]

d4

Process 2 from Figure 9-1

Microvia capture land size =

[(b + 2X min annular ring) + FA(1)]

300μm [12mil]

225μm [9mil]

175μm [7mil]

s

Print & Etch conductor trace width

100μm [4mil]

60μm [2.4mil]

50μm [2mil]

t

Print & Etch conductor spacing

100μm [4mil]

75μm [3mil]

50μm [2mil]

e5

Plated conductor trace width

100μm [4mil]

75μm [3mil]

50μm [2mil]

f5

Plated conductor spacing

100μm [4mil]

90μm [3.5mil]

60μm [2.4mil]

g

Through via land size =

[(h + 2X min annular ring) + FA(1)]

See 9.1.1 of IPC-2221

See 9.1.1 of IPC-2221

See 9.1.1 of IPC-2221

h

Through via diameter

(as formed, no plating)

See Table 5-2

See Table 5-2

See Table 5-2

i

Min thru via hole wall plating thickness

See IPC-2221, Table 4-3

See IPC-2221, Table 4-3

See IPC-2221, Table 4-3

j

Dielectric thickness

(HDI blind microvia layer)(2)

64μm [2.5mil]

64μm [2.5mil]

50μm [2mil]

k

Cu foil thickness to be Plated

(this represents the max foil thickness to achieve features “e” and “f” for one plating step)

1/2oz

(See IPC-2221, Table 10-2)

1/4oz

(See IPC-2221, Table 10-2)

1/8oz

(See IPC-2221, Table 10-2)

k’

Cu foil thickness for Print & Etch

(this represents the max foil thickness to achieve features “e” and “f” for one plating step)

1/2oz

(See IPC-2221, Table 10-1)

1/3oz

(See IPC-2221, Table 10-1)

1/4oz

(See IPC-2221, Table 10-1)

K

Total Copper Thickness at drill

K + plating present at drill

m

Min blind microvia hole plating thickness

12μm [4.7mil]

12μm [4.7mil]

12μm [4.7mil]

m’

Min buried microvia hole plating thickness

12μm [4.7mil]

12μm [4.7mil]

12μm [4.7mil]

n

Min buried via hole wall plating thickness

See IPC-2221

Table 4-3

See IPC-2221

Table 4-3

See IPC-2221

Table 4-3

o

Buried via diameter

(as formed, no plating)

See IPC-2221

Table 9-4

See IPC-2221

Table 9-4

See IPC-2221

Table 9-4

p

Buried via land size =

[(o + 2X annular ring) + FA(1)]

See 9.1.1 of IPC-2221

See 9.1.1 of IPC-2221

See 9.1.1 of IPC-2221

q

Buried via core thickness =

[(o + 2X annular ring) + FA(1)]

75μm[3mil]

50μm[2mil]

50μm[2mil]

r

Buried via Cu foil thickness

(outermost layer)

1/2oz

(See IPC-2221, Table 10-2)

1/4oz

(See IPC-2221, Table 10-2)

1/8oz

(See IPC-2221, Table 10-2)

u

Core board thickness

(excluding conductors)

75μm[3mil]

50μm[2mil]

50μm[2mil]

Note 1. FA = Fabrication Allowance which considers production master tooling and process variations required to fabricate printed circuit boards.

Note 2. Measured from top surface of Layer 2 Cu to bottom surface of Layer 1 Cu.

Note 3. Aspect Ratio 8:1 are not recommended for hole sizes less than 0.25mm [9.8mil] diameter.

Note 4. For process 1 described in Figure 9-1, Level A should be increased by 100μm [4mil] and Level B and Level C are not recommended.