Propagation Delay is the length of time taken for a signal to reach its destination in printed circuit boards (PCBs). To keep a good high-speed signal quality from driver to receiver on a PCB is not an easy task for designers. One of the most challenging issues is managing the propagation delay and relative time delay mismatches. To manage the time delays, we need to know how to calculate trace length from time delay value in order to implement the PCB trace routing accordingly.
Propagation Delay=84.6 x (εeff)½
εeff = Effective Dielectric Constant (Er or Dk)
For the formulation, in high speed PCB, the lowering the effective dielectric constant will increase the signal transmission speed. So, we need to choose low Dk materials, like Panasonic Megtron 6 (M6), Elite EM-355D and etc. Also see Signal Loss.
Much has been written about terminating PCB traces in their characteristic impedance, to avoid signal reflections. However, it may not be clear when transmission line techniques are appropriate. A good guideline to determine when the transmission line approach is necessary for logic signals is as follows:
Terminate the transmission line in its characteristic impedance when the one-way propagation delay of the PCB track is equal to or greater than one-half the applied signal rise/fall time (whichever edge is faster).
In electronics, digital circuits and digital electronics, the propagation delay, or gate delay, is the length of time which starts when the input to a logic gate becomes stable and valid to change, to the time that the output of that logic gate is stable and valid to change. Often on manufacturers’ datasheets this refers to the time required for the output to reach 50% of its final output level when the input changes to 50% of its final input level. Reducing gate delays in digital circuits allows them to process data at a faster rate and improve overall performance. The determination of the propagation delay of a combined circuit requires identifying the longest path of propagation delays from input to output and by adding each tpd time along this path.
The difference in propagation delays of logic elements is the major contributor to glitches in asynchronous circuits as a result of race conditions. The principle of logical effort utilizes propagation delays to compare designs implementing the same logical statement.
Propagation delay increases with operating temperature, as resistance of conductive materials tends to increase with temperature. Marginal increases in supply voltage can increase propagation delay since the upper switching threshold voltage, VIH (often expressed as a percentage of the high-voltage supply rail), naturally increases proportionately. Increases in output load capacitance, often from placing increased fan-out loads on a wire, will also increase propagation delay. All of these factors influence each other through an RC time constant: any increase in load capacitance increases C, heat-induced resistance the R factor, and supply threshold voltage increases will affect whether more than one time constants are required to reach the threshold. If the output of a logic gate is connected to a long trace or used to drive many other gates (high fanout) the propagation delay increases substantially.
Wires have an approximate propagation delay of 1 ns for every 6 inches (15 cm) of length. Logic gates can have propagation delays ranging from more than 10 ns down to the picosecond range, depending on the technology being used.