DRC

PCB Design Rule Check, more commonly called as DRC in the PCB industry, is a design process to determine if the layout satisfies a number of rules, and also a CAM process to determine whether your production data meets PCB manufacturing capabilities provided by the printed circuit board (PCB) manufacturer. Thus, DRC running can perform in design software and PCB manufacturing related CAM software. Without DRC, faulty PCBs or unnecessary delays in production can occur.

In this page, MADPCB only talk about PCB DRC in design process. For PCB DRC in manufacturing process, please refer to our DFM (Design for Manufacturability).

PCB designs commonly undergo multiple respins as a result of inconspicuous signal integrity (SI), power integrity (PI), and electro-magnetic interference (EMI) violations for ensuring that a given design meets it performance, time to market and cost goals. To help eliminate complicated and difficult-to-diagnose layout violations, some PCB tool suites offer unique electrical design rule checks (DRC).

When using DRC analysis as part of the PCB design process, engineers can ensure that their PCBs fall within the proper constrains for a multitude of different, advanced electrical design rules. The DRC tool constrains fully-customizable SI, PI, EMI, and safety rule checks that enable PCB designers to quickly identify and correct violations well before starting the manufacturing process. By running DRC analysis, it is possible to eliminate error-prone manual inspection and reduce costly design respins that impact the product’s time to market and the company’s profitability.

 

Combination of PCB DRC and PCB Layout

 

Because the layout and DRC tools are fully integrated, a PCB design can be loaded into DRC directly from the PCB layout window. The rules within DRC are sorted into specific categories—SI, PI, EMI, and safety. And each individual rule contains a descriptive overview page, making it easy for designers to select the most important tests to run on their PCB layout.

When a high-speed net crosses a split plane, it can create an impedance discontinuity on the signal trace, possibly leading to unwanted reflections, radiation, and crosstalk. With the increased complexity and density of today’s PCB designs, finding and reviewing all instances of a net crossing a split plane is a grueling manual process. Additionally, standard simulation tools do not typically check for those occurrences. When the nets crossing gaps rule is run in DRC, it is easy to pinpoint exactly where all instances of these discontinuities may appear.

 

PCB DRC Running

 

After running a rule, PCB designers can select the spreadsheet tab to display a list view of results for that DRC test. By clicking on a specific occurrence of a violation within the spreadsheet tab, the tool will jump to the exact location of that error on the PCB design. Any parts or traces associated with that violation will be highlighted.

With combination of PCB layout and DRC interfaces, the violation data from the DRC client will automatically load into the PCB layout tool. This allows PCB designers to their layout without having to manually cross reference between tools. To ensure that violations are cleared once changes have been made to the PCB design, the linked DRC client can be used to run, or rerun, any selected rules from directly within the layout tool window.

 

Testing Differential Pair Symmetry With PCB DRC

 

Your PCB design may contain a number of differential pairs, like 50ohm, 90ohm and 100ohm differential impedance. These differential pairs have been structured inside the layout tool’s constraint manager to be contained within a separate constraint class. Due to the tight integration between layout and DRC, the constraint class definitions created within the PCB tool will also be defined automatically within the DRC tool. In DRC, designers can quickly create an object list from the constraint class, allowing them to selectively choose to run the next rule on only those two differential nets.

When designing differential impedance traces, symmetry in the length, spacing, and via count/positions of the pairs is imperative for proper functionality. The differential pair rule will check whether these properties are consistent with in the proper bounds for all trace segments on a given net.

With DRC’s customizable properties, PCB designers can easily define rule parameters, such as target impedance on the traces and minimum and maximum allowable trace length. Because the specific differential traces that are being tested have a certain differential impedance, the target impedance parameter should be defined as the same before running the rule. DRC provides the flexibility to customize each rule for individual design parameters, thereby reducing false violation and giving designers more control.

 

PCB DRC Rules

 

A comprehensive design rule check helps recognizing many mistakes already in advance and to avoid reclamations.

 

• Checking Proper Placement of Decoupling Capacitors with DRC: One of the many challenges that engineers face on a regular basis is ensuring that their designs meet the defined specifications for each component. Manually checking the placement of decoupling capacitors on each net is a tedious and time-consuming process. Alternatively, the decoupling capacitor placement rule in DRC will locate all improperly placed, and non-existent, decoupling capacitors for a defined net or component.

 

• Vertical Plane Change Rule: Routing a trace from one layer to another is a common design practice used to accommodate today’s densely packed PCB layouts; however, care must be taken to reduce the risk of common-mode radiation. Frequently, stitching capacitors or stitching vias are placed near the net when a plane change occurs to allow for a continuous current return path. The vertical reference plane change rule identifies instances of signals transitioning from one layer to another as well as the placement of stitching capacitors or stitching vias near those nets.

 

• DDR Signals Delay and Length Matching Rule: Timing on high-speed nets is incredibly important for proper functionality, especially on DDR nets. If DDR signals do not reach their destination within proper timing constraints, the memory may now work properly. Timing issues occur for a multitude of reasons, including transmission line propagation delay due to layer stack-up, dielectric properties, and trace routing. Because delay issues are often caused by the unique physical properties of a PCB board, the delay and length matching rule can automatically calculate necessary values from the design’s layer stack-up and the check for equivalent delays and/or lengths on each net in a specific group.

 

• DDR Fly-by Topology Rule: In DDR designs that use fly-by topology, stub length is important for proper functionality. The fly-by topology rule checks to make sure that nets with fly-by topology are designed within the proper constraints.

 

• Crosstalk Coupling Rule: The crosstalk coupling rule will help identify areas on a design where unwanted crosstalk occurs on sensitive nets. Crosstalk can cause serious timing and functionality errors, and can also be very difficult to manually diagnose on a manufactured printed circuit board (PCB).

 

• Power/Ground Width Rule: The power/ground width rule checks for narrow trace and ground traces are not designed to be wide enough, the resulting current on that net can be insufficient. This may lead to a host of problems including, but not limited to, a lack of adequate power supplied to components as well as unnecessary heat production.

 

• Signal Supply Rule: The signal supply rule checks for discontinuities between an integrated component’s supply planes and its connected traces’ reference plane. These types of violations can lead to potentially strong radiation, and as a result, EMI failures.

 

• Filer Placement Rule: The filter placement rule checks for the presence of filters within a close enough proximity to a connector’s pins. To protect sensitive signals, as well as prevent radiation, filters are used to suppress noise that may be present on a connector. The absence, or misplacement, of filters on connectors can lead to serious EMI issues and failures.

 

• Return Path Rule: The return path rule ensures that the tested signals have a sufficiently low-impedance return path. With the increase in today’s high-speed circuit design requirements, as well as the decrease in PCB size, adhering to proper return path rules is incredibly important. If the return current on a trace not able to properly flow underneath the conductor. It can instead take an unintended path through other areas of your circuit, possibly resulting in EMI issues.

 

• Other Rules: Not list here. For more information of other DRC rules, just keep in touch with MADPCB professional design team.

 

With tightly combined PCB layout and DRC running, PCB designers can ensure that their PCBs will not fail as a result of unnoticed SI, PI, EMI, and safety violations. Editable parameters within PCB DRC allow users full control to adapt each test for their specific design requirements. With the aforementioned rules, in addition to many more, DRC can reassure designers that their PCBs will function properly while reducing costly board failures and design electrical rule expectations on the front end, companies can speed up their product’s time to market, and ultimately improve profitability.