A Bus is an electrical design primitive. It is a polyline object that represents a multi-wire connection. Buses are available for placement in the schematic editor in PCB design software. Modern computing simply wouldn’t be possible without PCB bus routing and layout. The same goes for many digital systems that manipulate data in parallel.
- Consistent trace impedance
- Proper termination
- A tight ground return path to minimize loop inductance
- Trace length matching for parallel buses
The same issue applies to routing a clock signal alongside your bus, whether it’s a common clock or source-synchronous clock. Embedded clocks, where a clock signal is encoded in the first few bits of your bitstream, do not incur problems with clock routing in PCB bus routing.
Using a common clock with a bus is more prone to mis-timed signalling as the number of driver/receiver ICs in series increases. This is because each IC contributes some jitter on the signal traces, and jitter adds in quadrature. Furthermore, each IC has some delay, and the clock lines from your common clock source need to be delay matched to account for the accumulated propagation delay. Suppressing jitter in the clock with a PLL is possible but not really practical, especially once we consider round-trip clocking on a bi-directional bus. As digital systems have become more complex, standardized ICs have moved to a source-synchronous or embedded clock scheme. With source-synchronous clocking, you still need to ensure that the clock is properly length matched so that the driver/receiver latches at the proper time.
One aspect of maintaining consistent signal/clock line lengths and consistent impedance is in how you route signals in your bus. Even at low data rates, you should try to minimize vias on your bus lines to prevent impedance discontinuities. If you do use vias on your bus lines, you may need to stagger your vias along the length of the trace in order to make enough room for the vias.
When routing a bus, you will most likely need to use right angle bends at some point. Most designers will state that you should never use right angle turns in a PCB layout due to the EMI that is created at the corner, and this would appear in a bus as well. Once a bus is broken out into individual traces, it follows logically that strong crosstalk would appear in a trace nearby the right angle corner. It is also said that a right angle bend causes the signal to reflect back towards the source.